UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 53

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
2.2
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower
Remark
DRST
DDO
AD0 to AD15
A0 to A15
A16 to A23
WAIT
WR0, WR1
RD
ASTB
CS0, CS2, CS3
HLDAK
HLDRQ
CLKOUT
Other port pins
The operation states of pins in the various operation modes are described below.
Pin Name
Pin States
2. Operates while alternate functions are operating.
3. The state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer or clock monitor, etc., the
5. In the on-chip debug mode, data is output from the DDO pin.
6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
7. Operates even in the HALT mode, during DMA operation.
8. The A0 to A15 pins are used in the separate bus mode.
Note 8
limit) when the power is turned on.
state of this pin differs according to the OCDM.OCDM0 bit setting.
Hi-Z High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
When Power Is
Low-level output
High-level output
Input without sampling (not acknowledged)
Turned On
Undefined
Pull down
Hi-Z
Hi-Z
Note 6
Note 1
Table 2-2. Pin Operation Status in Each Operation Mode
When Power Is
During Reset
Pull down
(Other than
Turned On)
Hi-Z
Hi-Z
Hi-Z
Note 5
Note 6
Note 4
CHAPTER 2 PIN FUNCTIONS
User’s Manual U19601EJ2V0UD
HALT Mode
Undefined
Undefined
Operating
Note 7
H
Held
Held
Held
Note 7
Note 7
Note 7
Note 2
IDLE1, IDLE2,
Sub-IDLE
Mode
Held
Held
Held
Hi-Z
H
L
Note 2
Mode
STOP
Held
Held
Held
Hi-Z
H
L
Note 2
Idle State
Operating
Held
Held
Held
Held
H
Note 3
Operating
Operating
Bus Hold
Held
Held
Held
Hi-Z
Hi-Z
L
51

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