UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 609

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

HZA0DCCn
HZA0DCFn
HZA0DCTn
• Pins can function as output pins when the HZA0DCM bit = 0, regardless of the
• If an edge indicating abnormality is input to the external pin (which is set by the
• The HZA0DCCn bit is always 0 when it is read.
• The HZA0DCCn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.
• If an edge indicating abnormality is input to the external pin (which is detected
• The HZA0DCTn bit is always 0 when it is read because it is a software-triggered
• The HZA0DCTn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.
status of the external pin.
HZA0DCNn and HZA0DCPn bits) when the HZA0DCM bit = 1, the HZA0DCCn
bit is invalid even if it is set to 1.
according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn
bit is invalid even if it is set to 1.
bit.
0
1
0
1
0
1
No operation
Pins are made to go into a high-impedance state by software and the
HZA0DCFn bit is set to 1.
No operation
Pins that have gone into a high-impedance state are output-enabled by
software and the HZA0DCFn bit is cleared to 0.
Indicates that output of the pin is enabled.
• This bit is cleared to 0 when the HZA0DCEn bit = 0.
• This bit is cleared to 0 when the HZA0DCCn bit = 1.
Indicates that the pin goes into a high-impedance state.
• This bit is set to 1 when the HZA0DCTn bit = 1.
• This bit is set to 1 when an edge indicating abnormality is input to the
external pin (which is detected according to the setting of the
HZA0DCNn and HZA0DCPn bits).
CHAPTER 11 MOTOR CONTROL FUNCTION
User’s Manual U19601EJ2V0UD
High-impedance output control clear bit
High-impedance output status flag
High-impedance output trigger bit
(2/2)
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