UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 753

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) UARTBn FIFO control register 0 (UBnFIC0)
Note After transmit FIFO is cleared (UBnTFC bit = 1), accessing the registers related to UARTBn is
Remark
The UBnFIC0 register is used to select the operation mode of UARTBn and the functions that become valid in
the FIFO mode (UBnMOD bit = 1). In the FIFO mode, it clears transmit FIFO/receive FIFO and specifies the
timing mode in which the transmission enable interrupt request signal (INTUBnTIT)/reception end interrupt
request signal (INTUBnTIR) is generated.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
prohibited for the duration of four cycles of f
confirmed by reading the UBnFIC0 register. If these registers are accessed, the operation is not
guaranteed.
UBnFIC0
f
(n = 0, 1)
XX
: Peripheral clock
After reset: 00H
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
UBnMOD
UBnMOD
UBnTFC
•
•
•
<7>
The UBnTFC bit is valid only in the FIFO mode (UBnMOD bit = 1), and is invalid
in the single mode (UBnMOD bit = 0).
When 1 is written to the UBnTFC bit, the pointer to transmit FIFO is cleared to 0.
In the pending mode (UBnITM bit = 0), the interrupt request signal (INTUBnTIT)
held pending is cleared
register (UBnTITIC) is not cleared to 0. Clear this bit to 0 as necessary.
When 0 is written to the UBnTFC bit, the status is retained. No operation, such
as clearing or setting, is executed.
When writing 1 to the UBnTFC bit, be sure to clear the UBnCTL0.UBnTXE bit to
0 (disabling transmission). If 1 is written to the UBnTFC bit when the UBnTXE
bit is 1 (transmission enabled), the operation is not guaranteed.
0
1
0
1
Single mode
FIFO mode
Normal status
Clear (This bit automatically returns to 0 after transmit FIFO is cleared.)
R/W
6
0
Address: UB0FIC0 FFFFFB8AH, UB1FIC0 FFFFFBAAH
User’s Manual U19601EJ2V0UD
5
0
Note
Specification of UARTBn operation mode
. However, bit 7 (UBnTITIF) of the interrupt control
Transmit FIFO clear trigger bit
XX
or until clearing the UBnTFC bit (automatic recovery) is
4
0
UBnTFC UBnRFC UBnITM
<3>
<2>
1
UBnIRM
0
(1/2)
751