UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1011

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1)
request is rejected and a start condition is not generated. There are two modes in which the bus is not used.
The time shown in Table 20-7 is required until the STCFn flag is set after setting the STTn bit to 1. Therefore, secure
the time by software.
When the IICCn.STTn bit is set when the bus is not being used for communication during bus communication, this
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
To confirm whether the start condition was generated or the request was rejected, check the IICFn.STCFn flag.
released when the IICCn.LRELn bit was set to 1) (n = 0 to 2)
OCKSENm
Remarks 1. ×: don’t care
1
1
1
1
0
2. n = 0 to 3 (V850ES/JH3-E)
OCKSm1
n = 0 to 4 (V850ES/JJ3-E)
m = 0 to 2
0
0
1
1
0
OCKSm0
Table 20-7. Wait Periods
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
0
1
0
1
0
CLn1
0
0
0
0
1
2
C BUS
CLn0
×
×
×
×
0
Wait Period
20 clocks
30 clocks
40 clocks
50 clocks
10 clocks
1009