UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 745

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UBnCTL0
(n = 1, 0)
After reset: 10H
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
UBnPWR
UBnPWR
UBnTXE
UBnRXE
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<7>
When the UBnPWR bit is cleared to 0, the UARTBn can be asynchronously reset.
When the UBnPWR bit = 0, UARTBn is in a reset state. Therefore, to operate
UARTBn, the UBnPWR bit must be set to 1.
When the UBnPWR bit is changed from 1 to 0, all registers of UARTBn are
initialized. When the UBnPWR bit is set to 1 again, the UARTBn registers must
be set again.
The TXDBn pin output is high level when the UBnPWR bit is cleared to 0.
On startup, set the UBnPWR bit to 1 and then set the UBnTXE bit to 1. To stop
transmission, clear the UBnTXE bit to 0 and then the UBnPWR bit to 0.
When the transmission unit status is to be initialized, the transmission status
may not be able to be initialized unless the UBnTXE bit is set to 1 again after an
interval of two cycles of f
On startup, set the UBnPWR bit to 1 and then set the UBnRXE bit to 1. To stop
reception, clear the UBnRXE bit to 0 and then the UBnPWR bit to 0.
When the reception unit status is to be initialized, the reception status may not
be able to be initialized unless the UBnRXE bit is set to 1 again after an interval
of two cycles of f
0
1
0
1
0
1
Stops supply of clocks to UARTBn
Supplies clocks to UARTBn
Transmission is disabled
Transmission is enabled
Reception is disabled
Reception is enabled
UBnTXE UBnRXE UBnDIR
R/W
<6>
XX
Address: UB0CTL0 FFFFFB80H, UB1CTL0 FFFFFBA0H
User’s Manual U19601EJ2V0UD
has elapsed since the UBnRXE bit was cleared to 0.
<5>
XX
has elapsed since the UBnTXE bit was cleared to 0.
Operation clock control to UARTBn
<4>
Transmission enable
Reception enable
UBnPS1 UBnPS0
3
2
UBnCL
1
UBnSL
0
(1/2)
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