UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 740

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

738
(12) UARTBn transmit data register (UBnTX)
(13) Timeout counter
(14) Sampling block
The transmit data register is a buffer for transmit data. The 8-bit × 1-stage UBnTX register is used as this
buffer in the single mode. In the FIFO mode, the 8-bit × 16-stage transmit FIFO is used.
When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of the transmit data register are transmitted
as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with
the MSB first, bits 7 to 1 of the transmit data register are transmitted as the transmit data from the MSB (bit 7)
with the LSB (bit 0) always being 0.
In the single mode, transmission is started by writing transmit data to the UBnTX register while transmission
is enabled (UBnCTL0.UBnTXE bit = 1). When writing the transmit data to the UBnTX register is enabled
(when 1-byte data is transferred from the UBnTX register to the transmit shift register), a transmission enable
interrupt request signal (INTUBnTIT) is generated.
In the FIFO mode, transmission is started by writing at least the number of transmit data set as the trigger by
the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16 bytes or less to transmit FIFO and then enabling
transmission (UBnTXE bit = 1).
UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits have been transferred from transmit FIFO to the transmit shift
register (transmit data of the number set as the trigger can be written), a transmission enable interrupt
request signal (INTUBnTIT) is generated. In the FIFO mode, a FIFO transmission enable interrupt request
signal (INTUBnTIF) is generated when there is no more data in transmit FIFO and the transmit shift register
(when FIFO and the register become empty).
This counter is used to recognize that data exists (remains) in receive FIFO when the number of received
data does not reach the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits, and is
valid only in the FIFO mode.
If data is stored in receive FIFO when the next data does not come (start bit is not detected) after the next
data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed after the
stop bit has been received, a reception timeout interrupt request signal (INTUBnTITO) is generated.
This block samples the RXDBn signal at the rising edge of the peripheral clock (f
value is detected two times, output of the match detector changes, and the value is sampled as input data.
Data of less than one clock width is judged as noise and is not transmitted to the internal circuitry.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
When the number of transmit data set as the trigger by the
XX
). If the same sampling