UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1644

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(3) Operation in STOP mode or after STOP mode is released
(4) Operation when main clock is stopped (arbitrary)
(5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1)
Internal oscillation
Internal oscillation
If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and
while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor
operation is automatically started.
During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to
1, the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor
operation is automatically started when the main clock operation is started.
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.
Clock monitor
Clock monitor
Main clock
Main clock
operation
operation
CLME
CLME
status
status
clock
clock
CPU
CPU
Figure 29-4. Operation in STOP Mode or After STOP Mode Is Released
operation
Normal
Figure 29-5. Operation When Main Clock Is Stopped (Arbitrary)
monitor
monitor
During
During
PCC.MCK bit = 1
Oscillation stops
Oscillation stops
Monitor stops
STOP
Subclock operation
CHAPTER 29 CLOCK MONITOR
User’s Manual U19601EJ2V0UD
Oscillation stabilization time
Monitor stops
Oscillation stabilization time
Oscillation stabilization time
Oscillation stabilization
time count by software
(set by OSTS register)
(set by OSTS register)
Monitor stops
Main clock operation
Normal operation
During monitor
During monitor