UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1487

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.5.3 Receive function
checks the length field and FCS, and identifies whether the frame is a VLAN frame.
number of times each event has occurred in all receive frames is counted by statistics counters.
The Ethernet controller generates a receive packet from a receive frame to be stored in the FIFO, detects the SFD,
The status information of each receive packet is set to the reception status monitor register (RXSTMONI) and the
(1) Receive clock
(2) Reception of MII data
(3) Detecting preamble and SFD
(4) Checking length field
(5) CRC
(6) Transmitting data to FIFO
(7) Detection of huge packet
(8) Detecting VLAN frame
The Ethernet controller receives data in synchronization with the reception clock (RXCLK) supplied by an
external (PHY) device.
IEEE802.3 specifies the frequency of RXCLK as 25 MHz±100 ppm when the data rate is 100 Mbps and 2.5
MHz±100 ppm at 10 Mbps.
The Ethernet controller recognizes data synchronized with the P1RXDV[3:0] signal as receive frames while the
P1RXDV signal is asserted, and recognizes the end of the frame when the P1RXDV signal is deasserted.
The Ethernet controller detects the preamble and SFD at the beginning of a receive frame and recognizes the
data that follows as a receive packet.
The Ethernet controller counts the length of a receive packet and checks the length of the data field, regarding
the 2 bytes following the source address as a length field. The result of this check can be read as the reception
status from the RXSTMONI register. If the result of checking is a mismatch, an interrupt signal can be
specified to be output.
The Ethernet controller calculates the 4-byte frame check sequence (FCS) from a receive packet and
compares it with the FCS data appended to the end of the receive packet. The result of the comparison can be
read from the RXSTMONI register. If the two FCS data do not match, an interrupt signal can be specified to be
output.
The Ethernet controller assumes that a packet of 6 bytes or more is valid and discards a packet of less than 6
bytes.
If the MACC1.HUGEN bit is set to 0, the Ethernet controller receives only a packet shorter than the maximum
frame length set by the LMAX register (default value: 1,536 bytes) and stops reception of a packet exceeding
this length midway.
For the length of receivable packets, refer to Table 23-14 Restrictions on Receive FIFO.
The Ethernet controller checks all the packets it has received to see whether they are a VLAN frame.
If the value of the TPID field (the 2 bytes following the source address) of the received packet matches the
value set to the VLTP register, the packet is recognized as a VLAN packet and the RXSTMONI.VLAN flag is set.
In packets recognized as a VLAN frame, the 2 bytes immediately after the VLAN header (4 bytes following the
source address) including the TPID field are regarded as the length field.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
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