UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1215

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) UF0 EPNAK register (UF0EN)
UF0EN
Bit position
This register controls NAK of endpoints other than Endpoint0.
This register can be read or written in 8-bit units (however, bits 5, 4, 1, and 0 can only be read).
The BKO2NK bit can be written only when the BKO2NKM bit of the UF0ENM register is 1 and the BKO1NK bit
can be written only when the BKO1NKM bit of the UF0ENM register is 1.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4,
7) and the current setting of the interface.
It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have
been set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the
UF0FIC0 and UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2,
UF0E0N, and UF0EN registers by at least four USB clocks.
While NAK is being transmitted to Endpoint0 Read, Endpoint2, and Endpoint4, a write access to the BKO1NK
and BKO2NK bits is ignored.
Be sure to clear bits 7 to 5 to “0”. If it is set to 1, the operation is not guaranteed.
4
7
0
IT1NK
Bit name
6
0
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
0
This bit controls NAK to Endpoint7 (interrupt 1 transfer).
It is automatically set to 1 and transmission is started when the UF0INT1 register has
become full as a result of writing data to it. To send a short packet that does not make
the FIFO full, set the IT1DEND bit of the UF0DEND register to 1. As soon as the
IT1DEND bit has been set to 1, this bit is automatically set to 1.
This bit is also cleared to 0 when the UF0INT1 register has been cleared.
1: Do not transmit NAK.
0: Transmit NAK (default value).
IT1NK
4
User’s Manual U19601EJ2V0UD
BKO2NK
3
BKO1NK
2
BKI2NK
Function
1
BKI1NK
0
00200004H
Address
After reset
00H
1213
(1/4)