UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 973

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.6 I
generated on the I
bit data).
pin’s low-level period can be extended and a wait state can be inserted (n = 0 to 2).
The following section describes the I
The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”
The master device generates the start condition, slave address, and stop condition.
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-
The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n
Remark
2
C Bus Definitions and Control Methods
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
SDA0n
SCL0n
2
C bus’s serial data bus is shown below.
Start
condition
Address
1 to 7
Figure 20-8. I
2
C bus’s serial data communication format and the signals used by the I
R/W
8
User’s Manual U19601EJ2V0UD
ACK
CHAPTER 20 I
2
C Bus Serial Data Transfer Timing
9
1 to 8
Data
2
C BUS
ACK
9
1 to 8
Data
ACK
9
Stop
condition
2
C bus.
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