UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 941

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.6.13 Reception error
the reception completion interrupt request signal (INTCFnR) is generated again when the next receive operation is
completed before the CFnRX register is read after the INTCFnR signal is generated, and the overrun error flag
(CFnSTR.CFnOVE) is set to 1.
if a reception error has occurred, the INTCFnR signal is generated again upon the next reception completion if the
CFnRX register is not read.
next receive data from the INTCFnR signal generation.
SIFn pin capture
INTCFnR signal
CFnRX register
CFnRX register
When transfer is performed with reception enabled (CFnCTL0.CFnRXE bit = 1) in the continuous transfer mode,
Even if an overrun error has occurred, the previous receive data is lost since the CFnRX register is updated. Even
To avoid an overrun error, complete reading the CFnRX register by one half clock before sampling the last bit of the
(1) Operation timing
Shift register
CFnOVE bit
read signal
SCKFn pin
SIFn pin
(1) Start continuous transfer.
(2) Completion of the first transfer
(3) The CFnRX register cannot be read until one half clock before the completion of the second transfer.
(4) An overrun error occurs, and the reception completion interrupt request signal (INTCFnR) is
Remark
timing
generated, and then the overrun error flag (CFnSTR.CFnOVE) is set to 1.
overwritten.
n = 0 to 4 (V850ES/JH3-E)
n = 0 to 6 (V850ES/JJ3-E)
(1)
01H
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
02H
05H 0AH 15H 2AH 55H AAH 00H 01H 02H 05H 0AH 15H 2AH 55H
User’s Manual U19601EJ2V0UD
(2)
AAH
(3)
(4)
The receive data is
55H
939