MC68EC000 Motorola, MC68EC000 Datasheet - Page 100

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

cycle. For all other exceptions, internal logic provides the vector number. This vector number
is then used to calculate the address of the exception vector.
The third step, except for the reset exception, is to save the current SCM68000 status. (The
reset exception does not save the context and skips this step.) The current program counter
value and the saved copy of the status register are stacked using the SSP. The stacked pro-
gram counter value usually points to the next unexecuted instruction. However, for bus error
and address error, the value stacked for the program counter is unpredictable and may be
incremented from the address of the instruction that caused the error. Group 1 and 2 excep-
tions use a short format exception stack frame. Additional information defining the current
context is stacked for the bus error and address error exceptions.
The last step is the same for all exceptions. The new program counter value is fetched from
the exception vector. The SCM68000 then resumes instruction execution at the address
provided by the exception vector, and normal instruction decoding and execution is started.
4.3 PROCESSING OF SPECIFIC EXCEPTIONS
The exceptions are classified according to their sources, and each type is processed differ-
ently. The following paragraphs describe in detail the types of exceptions and the processing
of each type.
4.3.1 Reset
The reset exception corresponds to the highest exception level. The processing of the reset
exception is performed for system initiation and recovery from catastrophic failure. If the
SCM68000 is currently executing a bus cycle, it will start processing at state 5 (S5) imme-
diately after the internal reset signal is valid. The bus cycle will end at state 7 (S7) and the
current instruction being executed will be canceled. The SCM68000 is forced into the super-
visor state, and the trace state is forced off. The interrupt priority mask is set to level seven.
The vector number is internally generated to reference the reset exception vector at location
zero in the supervisor program space. Because no assumptions can be made about the
validity of register contents, in particular the SSP, neither the program counter nor the status
register is saved. The address in the first two words of the reset exception vector is fetched
as the initial SSP, and the address in the last two words of the reset exception vector is
MOTOROLA
SSP
Figure 4-9. Groups 1 and 2 Exception Stack Frame
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PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
STATUS REGISTER
0
7
ODD BYTE
0
0
ADDRESS
HIGHER
Exception Processing
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