MC68EC000 Motorola, MC68EC000 Datasheet - Page 77

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
To achieve clock frequency independence at a system level, the bus can be operated in an
asynchronous manner. Asynchronous bus operation uses the bus handshake signals to
control the transfer of data. The handshake signals are ASB, UDSB, LDSB, DSB, DTACKB,
BERRB, HALTIB, and AVECB. ASB indicates the start of the bus cycle, and UDSB, LDSB,
and DSB signal valid data for a write cycle. After placing the requested data on the data bus
(read cycle) or latching the data (write cycle), the slave device (memory or peripheral)
asserts DTACKB to terminate the bus cycle. If no device responds or if the access is invalid,
external control logic asserts BERRB, or BERRB and HALTIB, to abort or retry the cycle.
Figure 3-29 shows the use of the bus handshake signals in a fully asynchronous read cycle.
Figure 3-30 shows a fully asynchronous write cycle.
In the asynchronous mode, the accessed device operates independently of the frequency
and phase of the system clock. For example, the MC68681 dual universal asynchronous
receiver/transmitter (DUART) does not require any clock-related information from the bus
master during a bus transfer. Asynchronous devices are designed to operate correctly with
processors at any clock frequency when relevant timing requirements are observed.
3-36
UDSB and/or LDSB
UDSB and/or LDSB
and DSB
DTACKB
D15–D0
and DSB
DTACKB
A31–A0
D15–D0
A31–A0
RWB
ASB
RWB
ASB
Figure 3-29. Fully Asynchronous Read Cycle
Figure 3-30. Fully Asynchronous Write Cycle
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
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