MC68EC000 Motorola, MC68EC000 Datasheet - Page 76

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

3.4.4 Double Bus Fault
When a bus error exception occurs, the SCM68000 begins exception processing by stack-
ing information on the supervisor stack. If another bus error occurs during exception pro-
cessing (i.e., before execution of another instruction begins) the SCM68000 halts and
asserts HALTOB. This situation is a double bus fault. Only an external reset operation can
restart a SCM68000 halted due to a double bus fault.
A retry operation does not initiate exception processing; a bus error during a retry operation
does not cause a double bus fault. The SCM68000 can continue to retry a bus cycle indef-
initely if external hardware requests.
A double bus fault occurs during a reset operation when a bus error occurs while the
SCM68000 is reading the vector table (before the first instruction is executed). The reset
operation is described in 4.3.1 Reset.
3.5 ASYNCHRONOUS OPERATION
All asynchronous input signals to the SCM68000 are synchronized before being used inter-
nally. As shown in Figure 3-28, synchronization requires a maximum of one cycle of the sys-
tem clock, assuming that the asynchronous input setup time (spec #47, defined in Section
7 Electrical Characteristics) has been met. The input asynchronous signal is sampled on
the falling edge of the clock and is valid internally after the next rising edge. The asynchro-
nous inputs are AVECB, RESETIB, HALTIB, DTACKB, BERRB, IPLB2–IPLB0, BRB, and
BGACKB.
MOTOROLA
Figure 3-28. External Asynchronous Signal Synchronization
BRB (EXTERNAL)
Freescale Semiconductor, Inc.
BRB (INTERNAL)
EC000 CORE PROCESSOR USER’S MANUAL
INTERNAL SIGNAL VALID
EXTERNAL SIGNAL SAMPLED
For More Information On This Product,
CLKI
Go to: www.freescale.com
47
Bus Operation
3-35