MC68EC000 Motorola, MC68EC000 Datasheet - Page 102

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

registers are affected by a RESET instruction. Figure 4-12 shows a timing diagram for
RESETOB.
If the RESETIB and RESETOB signals are connected as shown in Figure 4-10, the HALTIB
signal should not be asserted during the RESET instruction. When the SCM68000 recog-
nizes that both the HALTIB and RESETIB signals are asserted, it will begin the reset excep-
tion and negate RESETOB which will cause RESETIB to be negated. Since RESETIB would
not be asserted for at least ten clock periods with HALTIB, a partial reset will occur and may
drive the SCM68000 into an unknown state.
4.3.1.1.3 Reset Using Only RESETIB. The SCM68000 must initially be reset using the
RESETIB and HALTIB signals as previously described. However, subsequent resets can
also be accomplished by asserting only the RESETIB signal for a minimum of 132 clock peri-
ods.
Because an assertion of the RESETIB signal is ignored while the RESETOB signal is
asserted, the two signals can be connected as shown in Figure 4-10. Since the core may be
executing a RESET instruction at the time it is being reset using only the RESETIB signal,
the RESETIB signal should be asserted for a minimum of 132 clock periods. This will ensure
that the RESETOB signal has been negated and the RESETIB signal will be recognized.
MOTOROLA
BUS CYCLES
RESETIB
NOTES
HALTIB
1. Internal start-up time
2. SSP high read in here
3. SSP low read in here
V DD
V CC
CLKI
FOR 16-BIT MODE:
The user must ensure that all external devices are reset at the
completion of the RESET instruction. The RESETOB signal is
negated on the rising edge of S0 of the next bus cycle.
Figure 4-11. Reset Operation Timing Diagram
T 4 CLOCKS
Freescale Semiconductor, Inc.
4. PC High read in here
5. PC Low read in here
6. First instruction fetched here
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
T 132 CLOCK PERIODS
Go to: www.freescale.com
NOTE
All Three-State Signals in the
High-Impedance State.
All Control Signals Inactive.
Bus State Unknown:
Note1
Note 2
Note 3
Exception Processing
Note 4
Note 5
Note 6
4-17