MC68EC000 Motorola, MC68EC000 Datasheet - Page 71

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
3.4 BUS ERROR AND HALT OPERATION
In a bus architecture that requires a handshake from an external device, such as the asyn-
chronous bus used in the SCM68000, the handshake may not always occur. A bus error
input is provided to terminate a bus cycle in error when the expected signal is not asserted.
Different systems and different devices within the same system require different maximum
response times. External circuitry can be provided to assert the bus error signal after the
appropriate delay following the assertion of address strobe.
3.4.1 Bus Error Operation
A bus error is recognized when HALTIB is negated and BERRB is asserted, either alone or
with DTACKB.
When the bus error condition is recognized, the current bus cycle is terminated in state 9
(S9) (only BERRB is asserted) or in state 7 (S7) (BERRB and DTACKB are asserted) for a
read cycle or a write cycle. The bus cycle is terminated in state 11 (S11) for the read portion
of a read-modify-write cycle. For the write portion of a read-modify-write cycle, the bus cycle
is terminated in state 21 (S21) (only BERRB is asserted) or in state 19 (S19) (BERRB and
DTACKB are asserted). As long as BERRB remains asserted, the data bus is in the high-
impedance state. Figure 3-25 shows the timing for the normal bus error.
After the aborted bus cycle is terminated and BERRB is negated, the SCM68000 enters ex-
ception processing for the bus error exception. During the exception processing sequence,
the following information is placed on the supervisor stack:
The first two items are identical to the information stacked by any other exception. The
SCM68000 stacks bus error information to help determine and to correct the error.
After the SCM68000 has placed the required information on the stack, the bus error excep-
tion vector is read from vector table entry 2 (offset $08) and placed in the program counter.
The SCM68000 resumes execution at the address in the vector, which is the first instruction
in the bus error handler routine.
3-30
1. Status register
2. Program counter (two words, which may be up to five words past the instruction being
3. Error information
executed)
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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