MC68EC000 Motorola, MC68EC000 Datasheet - Page 33

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Signal Description
2.4.3 Upper and Lower Data Strobes (UDSB, LDSB), and Data Strobe
(DSB)
These active-low, three-state signals and RWB control the flow of data on the data bus.
Table 2-2 lists the combinations of these signals and the corresponding data on the bus.
When the RWB line is a logic high, the SCM68000 reads from the data bus. When the RWB
line is a logic low, the SCM68000 writes to the data bus. In the case of an 8-bit write in 16-
bit mode, the same data will be on both D7–D0 and D15–D8.
In 8-bit mode, UDSB is always forced high and only the LDSB signal and RWB are used to
control the flow of data on the data bus. Table 2-3 lists the combinations of these signals
and the corresponding data on the bus. When the RWB line is a logic high, the SCM68000
reads from the data bus. When the RWB line is a logic low, the SCM68000 drives the data
bus.
DSB is an active-low, three-state output signal that is asserted whenever LDSB or UDSB is
asserted.
2.4.4 Data Transfer Acknowledge (DTACKB)
This active-low input indicates the completion of the data transfer. When the SCM68000 rec-
ognizes DTACKB during a read cycle, data is latched and the bus cycle is terminated. When
DTACKB is recognized during a write cycle, the data bus enters a high-impedance state and
the bus cycle is terminated.
2.4.5 Data Transfer Size (SIZ1–SIZ0)
These active-high, three-state output signals provide information on the size of the operand
transfer. These outputs indicate the number of bytes to be transferred in the current bus
cycle. Table 2-4 indicates the size signal encoding.
2-4
Table 2-2. Upper and Lower Data Strobe Control of Data Bus
UDSB
High
High
High
Low
Low
Low
Low
Table 2-3. Lower Data Strobe Control of Data Bus
LDSB
High
Low
Low
LDSB
High
High
High
Low
Low
Low
Low
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RWB
High
High
High
Low
Low
Low
—
RWB
High
Low
—
No Valid Data
Valid Data Bits 15–8
No Valid Data
Valid Data Bits 15–8
Valid Data Bits 15-8
Valid Data Bits 7–0
Valid Data Bits 15–8
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No Valid Data
Read Cycle
Write Cycle
D15–D8
Data Bus Operation
No Valid Data
Valid Data Bits 7–0
Valid Data Bits 7–0
No Valid Data
Valid Data Bits 7–0
Valid Data Bits 7–0
Valid Data Bits 15–8
D7–D0
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