MC68EC000 Motorola, MC68EC000 Datasheet - Page 55

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
The descriptions of the read-modify-write cycle states are as follows:
STATE 0
STATE 1
3-14
The read cycle starts in state 0 (S0). The SCM68000 places valid function codes on FC2–
FC0 and a valid address on the address bus. RWB and ERWB are driven to a logic high
to identify a read cycle, and TSCAE is driven to a logic high to indicate that the SCM68000
is between bus cycles.
Entering state 1 (S1), TSCAE is driven low to indicate the beginning of the bus cycle, and
RMCB is driven low to indicate a read-modify-write cycle.
UDSB or LDSB
SIZ1–SIZ0
FC2–FC0
DTACKB
D15–D8
A31–A0
D7–D0
TSCAE
RMCB
ERWB
DOEB
AOEB
COEB
RWB
CLKI
DSB
ASB
Figure 3-13. Read-Modify-Write Cycle Timing Diagram
S0 S1 S2 S3 S4 S5 S6
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
INDIVISIBLE CYCLE
MOTOROLA