MC68EC000 Motorola, MC68EC000 Datasheet - Page 50

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

MOTOROLA
1) PLACE FUNCTION CODE ON FC2–FC0
2) PLACE ADDRESS ON A31–A0
3) ASSERT ADDRESS STROBE (ASB)
4) SET RWB AND ERWB TO WRITE
5) PLACE DATA ON D7–D0
6) ASSERT LOWER DATA STROBE (LDSB)
1) NEGATE LDSB AND DSB
2) NEGATE ASB
3) REMOVE DATA FROM D7–D0
4) SET RWB AND ERWB TO READ
1) PLACE FUNCTION CODE ON FC2–FC0
2) PLACE ADDRESS ON A31–A0
3) ASSERT ADDRESS STROBE (ASB)
4) SET RWB AND ERWB TO WRITE
5) PLACE DATA ON D7–D0 OR D15–D8
6) ASSERT UPPER DATA STROBE (UDSB)
1) NEGATE UDSB, LDSB, AND DSB
2) NEGATE ASB
3) REMOVE DATA FROM D7–D0 OR
4) SET RWB AND ERWB TO READ
AND DATA STROBE (DSB)
(ACCORDING TO A0)
OR LOWER DATA STROBE (LDSB) AND
DATA STROBE (DSB) (BASED ON A0)
D15–D8
TERMINATE OUTPUT TRANSFER
TERMINATE OUTPUT TRANSFER
ADDRESS THE DEVICE
ADDRESS THE DEVICE
START NEXT CYCLE
START NEXT CYCLE
Figure 3-9. Byte Write Cycle Flowchart for 16-Bit Mode
Figure 3-8. Byte Write Cycle Flowchart for 8-Bit Mode
BUS MASTER
BUS MASTER
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
1) DECODE ADDRESS
2) STORE DATA ON D7–D0
3) ASSERT DATA TRANSFER
1) NEGATE DTACKB
1) DECODE ADDRESS
2) STORE DATA ON D7–D0 IF LDSB IS
3) ASSERT DATA TRANSFER
1) NEGATE DTACKB
ACKNOWLEDGE (DTACKB)
ASSERTED. STORE DATA ON D15–D8
IF UDSB IS ASSERTED
ACKNOWLEDGE (DTACKB)
TERMINATE THE CYCLE
TERMINATE THE CYCLE
INPUT THE DATA
INPUT THE DATA
SLAVE
SLAVE
Bus Operation
3-9