MC68EC000 Motorola, MC68EC000 Datasheet - Page 83

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
ceeding clock period. The external signal has no defined phase relationship to the CPU
clock and may be changing at sampling time. Successful synchronization requires that the
internal machine receives a valid logic level (not a metastable signal), whether the input is
high, low, or in transition. Metastable signals propagating through synchronous machines
can produce unpredictable operation.
Parameter #47 of Section 7 Electrical Characteristics is the asynchronous input setup
time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling
edge of the system clock. However, signals that do not meet parameter #47 are not guar-
anteed to be recognized. In addition, if DTACKB is recognized on a falling edge, valid data
is latched into the SCM68000 (during a read cycle) on the next falling edge, provided the
data meets the setup time required (parameter #27). When parameter #27 has been met,
parameter #31 may be ignored. If DTACKB is asserted with the required setup time before
the falling edge of S4, no wait states are incurred, and the bus cycle runs at its maximum
speed of four clock periods.
3.7 THE RELATIONSHIP OF DTACKB, BERRB, AND HALTIB
To properly control termination of a bus cycle for a retry or a bus error condition, DTACKB,
BERRB, and HALTIB should meet the setup and hold time to the falling edge of the
SCM68000 clock. Specification #48 (see Section 7 Electrical Characteristics), can be
ignored when DTACKB, BERRB, and HALTIB are stable at the falling edge of the
SCM68000 clock.
The possible bus cycle termination can be summarized as follows (case numbers refer to
Table 3-1):
Table 3-1 shows the details of the resulting bus cycle termination for various combinations
of signal sequences.
3-42
• Normal Termination—DTACKB is asserted. BERRB and HALTIB remain negated (case
• Halt Termination—HALTIB is asserted coincident with or preceding DTACKB, and
• Bus Error Termination—BERRB is asserted in lieu of, coincident with, or preceding
• Retry Termination—HALTIB and BERRB are asserted in lieu of, coincident with, or be-
1).
BERRB remains negated (case 2).
DTACKB (case 3). HALTIB remains negated, and BERRB is negated coincident with or
after DTACKB.
fore DTACKB (cases 4, 5, and 6). BERRB is negated coincident with or after DTACKB.
HALTIB must be held at least one cycle after BERRB.
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EC000 CORE PROCESSOR USER’S MANUAL
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