MC68EC000 Motorola, MC68EC000 Datasheet - Page 85

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to unused address space. The timer
asserts BERRB after timeout (case 3).
EXAMPLE B:
A system uses error detection on random-access memory (RAM) contents. The system de-
signer may:
3-44
LEGEND:
*The BERRB and HALTIB signals are subject to the setup and hold time (spec #47, defined in Section 7 Electrical
Characteristics) before they are sampled on the falling edge of the previous state. “Negated” in this table refers to the
time when the signals are valid internally. See 3.5 Asynchronous Operation for more details on the external
asynchronous signal synchronization.
Termination in Table 3-1
none — Signal was not asserted.
1. Delay DTACKB until the data is verified. If data is invalid, return BERRB and HALTIB
2. Delay DTACKB until the data is verified. If data is invalid, return BERRB at the same
(cases 4, 5, and 6)
(cases 4, 5, and 6)
(cases 4, 5, and 6)
N — The number of the current even bus state (e.g., S4, S6, etc.)
• — Signal is negated in this bus state.
(cases 1 and 2)
(cases 1 and 2)
(cases 1 and 2)
(cases 1 and 2)
Conditions of
simultaneously to retry the error cycle (case 5).
time as DTACKB to take a bus error trap (case 3).
Bus Error
(case 3)
Normal
Normal
Normal
Normal
Rerun
Rerun
Rerun
Table 3-2. BERRB and HALTIB Negation Results
Signal Input
Control
HALTIB
HALTIB
HALTIB
HALTIB
HALTIB
HALTIB
HALTIB
HALTIB
BERRB
BERRB
BERRB
BERRB
BERRB
BERRB
BERRB
BERRB
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Rising Edge of
none
none
Go to: www.freescale.com
Negated on
N
•
•
•
•
•
•
•
•
•
•
State
*
N+2
•
•
•
•
May lengthen next cycle.
May lengthen next cycle.
If next cycle is started, it will be terminated as a bus error.
If next cycle is started, it will be terminated as a bus error.
Takes bus error trap.
Illegal sequence; usually traps to vector number 0.
Illegal sequence; usually traps to vector number 0.
Reruns the bus cycle.
Results—Next Cycle
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