MC68EC000 Motorola, MC68EC000 Datasheet - Page 101

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
fetched as the initial program counter. Finally, instruction execution is started at the address
in the program counter. The initial program counter should point to the power-up/restart
code.
The RESET instruction does not cause a reset exception; it asserts the RESETOB signal to
reset external devices, which allows the software to reset the system to a known state and
continue processing with the next instruction.
4.3.1.1 RESET OPERATION. The SCM68000 has an input reset signal (RESETIB) and an
output reset signal (RESETOB). In many cases, these two signals are connected to form
just one bi-directional RESETB signal. One way of combining these signals using cells from
the Motorola standard cell library is illustrated in Figure 4-10. The SCM68000 and it’s exter-
nal circuitry can be reset in three ways: asserting RESETIB and HALTIB simultaneously,
asserting only RESETIB, and using the RESET instruction. The methods to reset the
SCM68000 and it’s external devices are described in the following paragraphs.
4.3.1.1.1 Reset Using RESETIB and HALTIB. For the initial reset, RESETIB and HALTIB
must be asserted by an external device for at least 132 clock periods. Resetting the
SCM68000 initializes the internal state. The SCM68000 reads the reset vector table entry
(address $00000) and loads the contents into the SSP. Next, the SCM68000 loads the con-
tents of address $00004 (vector table entry 1) into the program counter. Then the
SCM68000 initializes the status registers by setting the supervisor state, clearing the trace
mode bit, and setting the interrupt mask level to seven. No other register is affected by the
reset sequence. The internal circuitry may cause the SCM68000 to take up to four clock
periods to recognize that a reset is taking place. The timings for the intial reset operation are
shown in Figure 4-11.
Subsequent resets can be accomplished by asserting RESETIB and HALTIB simulta-
neously for ten or more clock periods.
4.3.1.1.2 Reset Instruction. The RESET instruction causes the SCM68000 to assert
RESETOB for 124 clock periods to reset the external devices of the system. The internal
state of the SCM68000 is not affected. Neither the status register nor any of the internal
4-16
RESETOB
RESETIB
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Figure 4-10. Reset Circuit
Go to: www.freescale.com
IOBUF
INBUF
IOPD
RESETB
MOTOROLA