MC68EC000 Motorola, MC68EC000 Datasheet - Page 135

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Electrical Characteristics
7.7 AC ELECTRICAL SPECIFICATIONS—SCM68000 TO EXTERNAL
7-6
NOTE:
1.The falling edge of S6 triggers both the negation of the strobes (ASB and DSB) and the falling edge of TESTCLK. Either
of these events can occur first, depending upon the loading on each signal. Specificaton #49 indicates the absolute
maximum skew that will occur between the rising edge of the strobes and the falling edge of TESTCLK.
DATA OUT
Num
TESTCLK
49
DATA IN
12
18
20
23
27
29
41
42
44
45
47
50
51
54
A31–A0
AVECB
1
RWB
CLKI
ASB
PERIPHERALS
(Frequency = 0 to 20 MHz; GND = 0 Vdc; T A = T L to T H ; refer to Figure 7-4)
Clock Low to ASB, DSB Negated
Clock High to RWB High (Read)
Clock High to RWB Low (Write)
Clock Low to Data-Out Valid (Write)
Data-In Valid to Clock Low (Setup Time on Read)
ASB, DSB Negated to Data-In Invalid (Hold Time on Read)
Clock Low to TESTCLK Transition
TESTCLK Output Rise and Fall Time
ASB, DSB Negated to AVECB Negated
TESTCLK Low to Control, Address Bus Invalid (Address Hold
Time)
Asynchronous Input Setup Time
ASB, DSB Negated to TESTCLK Low
TESTCLK Width High
TESTCLK Width Low
TESTCLK Low to Data-Out Invalid
S0
18
Figure 7-4. SCM68000 to External Peripherals Timing Diagram
S1
S2
41
42
S3
S4
Characteristic
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
w
For More Information On This Product,
20
w
23
51
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Go to: www.freescale.com
47
w
w
w
w
41
w
w
Min
–30
190
290
w
10
—
—
—
1
0
0
5
0
0
5
5
42
3.3 V
w
w
Max
20
20
20
20
—
—
20
12
42
—
—
30
—
—
—
50
27
Min
–30
190
290
10
—
—
—
1
0
0
0
5
5
0
5
S5
12
41
5.0 V
S6
MOTOROLA
Max
S7
18
18
20
18
18
12
42
30
—
—
—
—
—
—
—
S0
29
49
Unit
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
44
45
54
18