MC68EC000 Motorola, MC68EC000 Datasheet - Page 49

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
STATE 9
3.1.2 Write Cycle
During a write cycle, the SCM68000 sends data to the memory or to a peripheral device.
The word write cycle flowchart is shown in Figure 3-7. The byte write cycle flowcharts for the
8-bit and 16-bit modes are shown in Figure 3-8 and Figure 3-9, respectively. The byte write
cycle timing diagram for the 8-bit mode of operation is shown in Figure 3-10. The word and
byte write cycle for the 16-bit mode of operation is shown in Figure 3-11.
3-8
During state 9 (S9), ASB, UDSB, LDSB, and DSB are negated. The device negates
BERRB at this time.
1) PLACE FUNCTION CODE ON FC2–FC0
2) PLACE ADDRESS ON A31–A0
3) ASSERT ADDRESS STROBE (ASB)
4) SET RWB AND ERWB TO WRITE
5) PLACE DATA ON D15–D0
6) ASSERT UPPER DATA STROBE
1) NEGATE UDSB, LDSB, AND DSB
2) NEGATE ASB
3) REMOVE DATA FROM D15–D0
4) SET RWB AND ERWB TO READ
(UDSB), LOWER DATA STROBE (LDSB),
AND DATA STROBE (DSB)
TERMINATE OUTPUT TRANSFER
ADDRESS THE DEVICE
START NEXT CYCLE
Figure 3-7. Word Write Cycle Flowchart for 16-Bit Mode
BUS MASTER
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
1) NEGATE DTACKB
1) DECODE ADDRESS
2) STORE DATA ON D15–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACKB)
TERMINATE THE CYCLE
INPUT THE DATA
SLAVE
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