MC68EC000 Motorola, MC68EC000 Datasheet - Page 98

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

4.2.2 Kinds of Exceptions
Exceptions are generated internally or externally, depending on the reason for the excep-
tion. The external exceptions are generated by interrupts, bus errors, and a reset. The inter-
rupts are requests from peripheral devices for SCM68000 action. For interrupt requests, the
peripheral must provide an 8-bit vector number on data bus lines D7-D0 (see Figure 4-8).
The bus error and reset inputs are used for access control and SCM68000 restart.
The internal exceptions are generated by instructions, address errors, or tracing. The trap
(TRAP), trap on overflow (TRAPV), check register against bounds (CHK), and divide (DIV)
instructions can generate exceptions as part of their instruction execution. In addition, illegal
instructions, word access to odd addresses, and privilege violations initiate exceptions.
Tracing is similar to a very high priority interrupt which is internally generated following each
instruction.
4.2.3 Multiple Exceptions
These paragraphs describe the processing that occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped by their occurrence and priority. Group 0 excep-
tions are reset, bus error, and address error. These exceptions cause the instruction cur-
rently being executed to abort and the exception processing to commence within two clock
cycles. Group 1 exceptions are trace and interrupt, privilege violations, and illegal instruc-
tions. Trace and interrupt exceptions allow the current instruction to execute to completion,
but pre-empt the execution of the next instruction by forcing exception processing to occur.
A privilege-violating instruction or an illegal instruction is detected when it is the next instruc-
tion to be executed. Group 2 exceptions occur as part of the normal processing of instruc-
tions. TRAP, TRAPV, CHK, and divide-by-zero exceptions are in this group. For these
exceptions, normal execution of an instruction may lead to exception processing.
Group 0 exceptions have the highest priority and group 2 exceptions have the lowest prior-
ity. Within group 0, reset has the highest priority, followed by address error and then bus
error. Within group 1, trace has priority over external interrupts, which in turn takes priority
over illegal instruction and privilege violation. Since only one instruction can be executed at
a time, no priority relationship applies within group 2.
The priority relationship between two exceptions determines which is taken, or taken first, if
the conditions for both arise simultaneously. Therefore, if a bus error occurs during a TRAP
instruction, the bus error takes precedence, and TRAP instruction processing is aborted. In
another example, if an interrupt request occurs during the execution of an instruction while
the T-bit is asserted, the trace exception has priority and is processed first. Before instruc-
tion execution resumes, however, the interrupt exception is also processed, and instruction
MOTOROLA
Where V7 is the MSB of the vector number and v0 is the LSB of the vector number.
D15
IGNORED
Figure 4-8. Interrupt Vector Number Format
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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D8
D7
V7
D6
V6
D5
V5
D4
V4
D3
V3
Exception Processing
D2
V2
D1
V1
4-13
D0
V0