MC68EC000 Motorola, MC68EC000 Datasheet - Page 87

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
4.1.1 Supervisor Mode
The supervisor mode has the higher level of privilege. The mode of the SCM68000 is deter-
mined by the S-bit of the status register; if the S-bit is set, the SCM68000 is in the supervisor
mode. All instructions can be executed in the supervisor mode. The bus cycles generated
by instructions executed in the supervisor mode are classified as supervisor references.
While the SCM68000 is in the supervisor mode, those instructions that use either the system
stack pointer implicitly or address register seven explicitly access the SSP.
4.1.2 User Mode
The user mode has the lower level of privilege. If the S-bit of the status register is clear, the
SCM68000 is executing instructions in the user mode.
Most instructions execute identically in either mode. However, some instructions having
important system effects are designated privileged. For example, user programs are not
permitted to execute the STOP instruction or the RESET instruction. To ensure that a user
program cannot enter the supervisor mode except in a controlled manner, the instructions
that modify the entire status register are privileged. To aid in debugging system software,
the move to user stack pointer (MOVE to USP) and move from user stack pointer (MOVE
from USP) instructions are privileged.
The bus cycles generated by an instruction executed in user mode are classified as user
references. Classifying a bus cycle as a user reference allows an external memory manage-
ment device to control access to protected portions of the address space. While the
SCM68000 is in the user mode, those instructions that use either the system stack pointer
implicitly or address register seven explicitly access the USP.
4.1.3 Privilege Mode Changes
The transition from supervisor to user mode can be accomplished by any of four instructions:
return from exception (RTE), move to status register (MOVE to SR), AND immediate to sta-
tus register (ANDI to SR), and exclusive OR immediate to status register (EORI to SR). The
RTE instruction fetches the new status register and program counter from the supervisor
stack and loads each into its respective register. Next, it begins the instruction fetch at the
new program counter address in the privilege mode determined by the S-bit of the new con-
tents of the status register.
Once the SCM68000 is in the user mode and is executing instructions, only exception pro-
cessing can change the privilege mode. During exception processing, the current state of
the S-bit of the status register is saved, and the S-bit is set, putting the SCM68000 in the
supervisor mode. Therefore, when instruction execution resumes at the address specified
to process the exception, the SCM68000 is in the supervisor privilege mode.
The MOVE to SR, ANDI to SR, and EORI to SR instructions fetch all operands in the super-
visor mode, perform the appropriate update to the status register, and then fetch the next
instruction at the next sequential program counter address in the privilege mode determined
by the new S-bit. The instruction following the MOVE/ANDI/EORI SR instruction will be
fetched twice, once from the old FC space and again from the new FC space (even if the S-
4-2
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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