MC68EC000 Motorola, MC68EC000 Datasheet - Page 136

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

7.8 AC ELECTRICAL SPECIFICATIONS—BUS ARBITRATION
MOTOROLA
NOTES:
1.Setup time for the synchronous inputs BGACKB , IPLB2 – IPLB0 , and AVECB guarantees their recognition at the next
falling edge of the clock.
2.BRB need fall at this time only in order to insure being recognized at the end of the bus cycle.
3.The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting
BGACKB.
4.The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be
reasserted.
37A
Num
58A
57A
36
58
33
34
35
37
38
39
46
47
57
7
2,4
1
3
(Frequency = 0 to 20 MHz; GND = 0 Vdc, T A = T L to T H ; see Figure 7-5 through Figure 7-8)
3
STROBES
AND RWB
Clock High to Address, Data Bus High Impedance (Maximum)
Clock High to BGB Asserted
Clock High to BGB Negated
BRB Asserted to BGB Asserted
BRB Negated to BGB Negated
BGACKB Asserted to BGB Negated
BGACKB Asserted to BRB Negated
BGB Asserted to Control, Address, Data Bus High Impedance
(ASB Negated)
BGB Width Negated
BGACKB Width Low
Asynchronous Input Setup Time
BGACKB Negated to ASB, DSB, RWB Driven
BGACKB Negated to FC Driven
BRB Negated to ASB , DSB, RWB Driven
BRB Negated to FC Driven
BGACKB
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERRB, BGACKB, BRB, DTACKB,
CLKI
BGB
BRB
IPLB2–IPLB0, and AVECB guarantees their recognition at the next falling edge of the clock.
Figure 7-5. Bus Arbitration Timing Diagram
Freescale Semiconductor, Inc.
Characteristic
35
EC000 CORE PROCESSOR USER’S MANUAL
33
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38
37
34
46
37A
10 ns
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
—
—
0
0
5
1
1
3.3 V
39
1.5 Clks
Max
3.5
3.5
3.5
25
25
25
42
—
—
—
—
—
—
—
Electrical Characteristics
10 ns
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
—
—
0
0
5
1
1
36
5.0 V
1.5 Clks
Max
3.5
3.5
3.5
20
25
25
42
—
—
—
—
—
—
—
Unit
Clks
Clks
Clks
Clks
Clks
Clks
Clks
Clks
Clks
ns
ns
ns
ns
ns
—
7-7