MC68EC000 Motorola, MC68EC000 Datasheet - Page 32

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

listed in the Section 7 Electrical Characteristics . The CLKO output follows CLKI to provide
a reference for testing.
2.4 ASYNCHRONOUS BUS CONTROL
The following signals control asynchronous data transfers: address strobe, read/write, early
read/write, data strobe, upper data strobe, lower data strobe, read-modify-write, data trans-
fer size, and data transfer acknowledge. These signals are described in the following para-
graphs.
2.4.1 Address Strobe (ASB)
This active low, three-state signal indicates that the information on the address bus is a valid
address.
2.4.2 Read/Write (RWB) and Early Read/Write (ERWB)
The active-low, three-state RWB output signal defines the data bus transfer as a read or
write cycle. The active-low, three-state ERWB output signal indicates a write cycle one-half
clock cycle earlier than the read/write signal. Negation times are the same for both signals.
These signals relate to the data strobe signals described in the following paragraphs.
MOTOROLA
Data Strobe
Data Transfer Acknowledge
Early Read Write
Function Code
Halt In
Halt Out
Interrupt Pending
Interrupt Control
Lower Data Strobe
Mode
CPU Pipe Refill
Reset In
Reset Out
Read-Modify-Write
Read/Write
Data Transfer Size
Microsequencer Status Indication
Stop
Test
Test Clock
Address Three-State Control
Upper Data Strobe
NOTE: TS = Three-State Output
STD = Standard CMOS Output
Signal Name
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
IPLB2–IPLB0
Mnemonic
RESETOB
SIZ1, SIZ0
STATUSB
TESTCLK
FC2–FC0
RESETIB
DTACKB
HALTOB
REFILLB
IPENDB
HALTIB
TSCAE
ERWB
MODE
RMCB
Table 2-1. Signal Summary
UDSB
LDSB
STOP
TEST
RWB
DSB
Go to: www.freescale.com
Input/ Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Active
State
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Output
Circuit
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
TS
TS
TS
TS
TS
TS
TS
TS
Instruction
HALTIB or
Hi-Z on
STOP
N/A
N/A
N/A
N/A
N/A
N/A
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Signal Description
Hi-Z on Bus
or RESETIB
Relinquish
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
N/A
N/A
N/A
N/A
N/A
No
No
No
No
No
No
No
No
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