MC68EC000 Motorola, MC68EC000 Datasheet - Page 103

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
4.3.1.2 INITIALIZING THE SCM68000 FOR SIMULATION. To simulate the SCM68000
properly, the initialization procedure differs slightly from the actual part. This difference is
necessary to correctly start the test clock (TESTCLK). Both HALTIB and RESETIB must be
asserted for at least 10 clock cycles. The TEST signal must be asserted for at least two clock
cycles while HALTIB and RESETIB are asserted and must be negated at least two clock
cycles before HALTIB and RESETIB are negated. Figure 4-13 shows the timing for initializ-
ing the SCM68000 for simulation.
If the SCM68000 has been properly reset during simulation, the TESTCLK signal will pulse
with a period equal to ten SCM68000 clock periods. The period will consist of six SCM68000
clock periods in the low position and four SCM68000 clock periods in the high position.
4-18
UDSB/LDSB
SIZ1–SIZ0
RESETOB
FC2–FC0
DTACKB
D15–D0
A31–A0
TSCAE
ERWB
AOEB
COEB
DOEB
RMCB
CLKI
RWB
DSB
ASB
S4 S5 S6
Figure 4-12. RESETOB Timing Diagram
S7 S0 S1 S2 S3
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
S4 S5 S6
RESET INSTRUCTION (132 CLOCK CYCLES)
S7
124 CLOCK CYCLES
MOTOROLA
S0 S1