MC68EC000 Motorola, MC68EC000 Datasheet - Page 73

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
3.4.2 Retrying the Bus Cycle
The assertion of BERRB during a bus cycle in which HALTIB is also asserted by an external
device initiates a retry operation. Figure 3-26 is a timing diagram of the retry operation.
The SCM68000 terminates the bus cycle, then puts the data bus in the high-impedance
state. The SCM68000 remains in this state until HALTIB is negated. Then the SCM68000
retries the preceding cycle using the same function codes, address, and data (for a write
operation). BERRB should be negated at least one clock cycle before HALTIB is negated.
3.4.3 Halt Operation
HALTIB performs a halt/run/single-step operation similar to the halt operation of an
MC68000. When HALTIB is asserted by an external device, the SCM68000 halts and
remains halted as long as the signal remains asserted, as shown in Figure 3-27.
While the SCM68000 is halted, only the data bus is placed in the high-impedance state as
shown in Table 2-1. Bus arbitration is performed as usual. Should a bus error occur while
HALTIB is asserted, the SCM68000 performs the retry operation previously described.
The single-step mode is derived from correctly timed transitions of HALTIB. HALTIB is
negated to allow the SCM68000 to begin a bus cycle, then asserted to enter the halt mode
when the cycle completes. The single-step mode proceeds through a program one bus cycle
at a time for debugging purposes. The halt operation and the hardware trace capability allow
tracing of either bus cycles or instructions one at a time. These capabilities and a software
debugging package provide total debugging flexibility.
3-32
To guarantee that the entire read-modify-write cycle runs cor-
rectly and that the write portion of the operation is performed
without negating the address strobe, the SCM68000 does not
retry a read-modify-write cycle. When BERRB is asserted during
a read-modify-write operation, a bus error operation is per-
formed whether or not HALTIB is asserted.
Execution of the RESET instruction while using the HALTIB sig-
nal in the single-step mode can cause the SCM68000 to reset.
4.3.1 Reset has more detailed information about the RESET in-
struction.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
NOTE
NOTE
MOTOROLA