MC68EC000 Motorola, MC68EC000 Datasheet - Page 84

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

The negation of BERRB and HALTIB under several conditions is shown in Table 3-2.
DTACKB is assumed to be negated normally in all cases. For reliable operation, both
DTACKB and BERRB should be negated when address strobe is negated.
Table 3-2 shows when BERRB and HALTIB should be negated with respect to when they
were asserted to produce various results. The first column describes which case in Table 3-
1 is being used for asserting the signals. The third column shows the current bus state and
the fourth column shows the following bus state. The last column describes what will happen
in the next bus cycle given the conditions described in the previous columns.
MOTOROLA
LEGEND:
*
#47, defined in Section 7 Electrical Characteristics) before they are sampled on the
falling edge of the previous state. “Asserted” in this table refers to the time when the sig-
nals are valid internally. See 3.5 Asynchronous Operation for more details on external
asynchronous signal synchronization.
The DTACKB, BERRB, and HALTIB signals are subject to the setup and hold time (spec
Case
Table 3-1. DTACKB, BERRB, and HALTIB Assertion Results
No.
1
2
3
4
5
6
NA — Signal not asserted in this bus state
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
Signal Input
DTACKB
DTACKB
DTACKB
DTACKB
DTACKB
DTACKB
Control
HALTIB
HALTIB
HALTIB
HALTIB
HALTIB
HALTIB
BERRB
BERRB
BERRB
BERRB
BERRB
BERRB
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Rising Edge of
Asserted on
A/S
NA
NA
NA
NA
NA
NA
NA
NA
N
A
A
X
A
A
X
A
A
A
Go to: www.freescale.com
State
N+2
*
NA
S
X
X
S
X
S
X
S
X
S
A
X
S
S
X
A
S
Normal cycle terminate and continue.
Normal cycle terminate and halt. Continue
when HALTIB negated.
Terminate and take bus error trap.
Terminate and retry when HALTIB negated.
Terminate and retry when HALTIB negated.
Terminate and retry when HALTIB negated.
Result
Bus Operation
3-43