MC68EC000 Motorola, MC68EC000 Datasheet - Page 110

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

SECTION 5
8-BIT INSTRUCTION EXECUTION TIMES
This section contains listings of the instruction execution times in terms of external clock
(CLKI) periods for the SCM68000 (EC000 core)
that both memory read and write cycles consist of four clock periods. A longer memory cycle
causes the generation of wait states that must be added to the total instruction times.
The number of bus read and write cycles for each instruction is also included with the timing
data. This data is shown as
where:
For example, a timing number shown as 18(3/1) means that 18 clock periods are required
to execute the instruction. Of the 18 clock periods, 12 are used for the three read cycles (four
periods per cycle). Four additional clock periods are used for the single write cycle, for a total
of 16 clock periods. The bus is idle for two clock periods during which the processor com-
pletes the internal operations required for the instruction.
5.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES
Table 5-1 lists the numbers of clock periods required to compute the effective addresses for
instructions. The totals include fetching any extension words, computing the address, and
fetching the memory operand. The total number of clock periods, the number of read cycles,
and the number of write cycles (zero for all effective address calculations) are shown in the
previously described format.
1.
MOTOROLA
The SCM68000 is the name of the Verilog model for the EC000 core. The remainder of this section will refer
to the part as only the SCM68000.
n is the total number of clock periods
r is the number of read cycles
w is the number of write cycles
The total number of clock periods (n) includes instruction fetch
and all applicable operand fetches and stores.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
NOTE
n(r/w)
1
in 8-bit mode. In this data, it is assumed
5-1