MC68EC000 Motorola, MC68EC000 Datasheet - Page 53

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
STATE 2
STATE 3
STATE 4
CASE 1: DTACKB is received alone or with BERRB (see 3.4 Bus Error and Halt Opera-
tion ).
STATE 5
STATE 6
STATE 7
CASE 2: BERRB is received without DTACKB (see 3.4 Bus Error and Halt Operation ).
STATE 5
STATE 6
STATE 7
STATE 8
3-12
On the rising edge of state 2 (S2), the SCM68000 asserts ASB and drives RWB to a logic
low.
During state 3 (S3), the data bus is driven out of the high-impedance state as data is
placed on the bus.
At the rising edge of state 4 (S4), the SCM68000 asserts DSB, and UDSB and/or LDSB.
The SCM68000 waits for a cycle termination signal (DTACKB or BERRB). If neither ter-
mination signal is asserted before the falling edge at the end of S4, the SCM68000 inserts
wait states (full clock cycles) until either DTACKB or BERRB is asserted. See 3.7 The Re-
lationship of DTACKB, BERRB, and HALTIB for a description of how DTACKB and
BERRB interact.
During state 5 (S5), no bus signals are altered.
During state 6 (S6), no bus signals are altered.
On the falling edge of the clock entering state 7 (S7), the SCM68000 negates ASB, UDSB,
LDSB, and DSB. As the clock rises at the end of S7, the SCM68000 places the data bus
in the high-impedance state and drives RWB and ERWB to a logic high. The device ne-
gates DTACKB or BERRB at this time.
During state 5 (S5), no bus signals are altered.
During state 6 (S6), no bus signals are altered.
During state 7 (S7), no bus signals are altered.
During state 8 (S8), no bus signals are altered.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA