MC68EC000 Motorola, MC68EC000 Datasheet - Page 104

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

4.3.2 Interrupts
Seven levels of interrupt priorities are provided, numbered 1–7. Devices can be chained
externally within interrupt priority levels, allowing an unlimited number of peripheral devices
to interrupt the SCM68000. The status register contains a 3-bit mask indicating the current
interrupt priority, and interrupts are inhibited for all priority levels less than or equal to the
current priority.
An interrupt request is made to the SCM68000 by encoding the interrupt request levels 1–
7 on the three interrupt request lines (IPLB2–IPLB0); all negated lines indicate no interrupt
request. Interrupt requests arriving at the SCM68000 do not force immediate exception pro-
cessing, but the requests are made pending. Pending interrupts are detected between
instruction executions. If the priority of the pending interrupt is lower than or equal to the cur-
rent SCM68000 priority, execution continues with the next instruction, and the requesting
interrupt is postponed until the priority of the pending interrupt becomes greater than the cur-
rent SCM68000 priority.
If the priority of the pending interrupt is greater than the current SCM68000 priority, the
exception processing sequence for the requesting interrupt is started. A copy of the status
register is saved; the privilege mode is set to supervisor mode; tracing is suppressed; and
the SCM68000 priority level is set to the level of the interrupt being acknowledged. The
SCM68000 fetches the vector number from the interrupting device by executing an interrupt
acknowledge cycle, which displays the level number of the interrupt being acknowledged on
the address bus. If external logic requests an automatic vector, the SCM68000 internally
generates a vector number corresponding to the interrupt level number. If external logic indi-
cates a bus error, the interrupt is considered spurious, and the generated vector number ref-
erences the spurious interrupt vector. The SCM68000 then proceeds with the usual
exception processing, saving the program counter and status register on the supervisor
stack. The saved value of the program counter is the address of the instruction that would
have been executed had the interrupt not been taken. The appropriate interrupt vector is
fetched and loaded into the program counter, and normal instruction execution commences
in the interrupt handling routine.
MOTOROLA
RESETIB
HALTIB
Figure 4-13. Initialization of the SCM68000 for Simulation Timing Diagram
TEST
CLKI
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0 CLOCK PERIODS
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
T
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10 CLOCK PERIODS
2 CLOCK PERIODS
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2 CLOCK PERIODS
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Exception Processing
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