MC68EC000 Motorola, MC68EC000 Datasheet - Page 7

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

2.8
2.8.1
2.8.2
2.8.3
2.9
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
2.9.6
2.10
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.6
3.7
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.5.1
4.1.5.2
4.2
4.2.1
viii
Table of Contents
Three-State Control ...................................................................................... 2-8
Processor Status .......................................................................................... 2-8
Multiplexing Pins........................................................................................... 2-9
Data Transfer Operations ............................................................................. 3-1
Bus Arbitration ............................................................................................ 3-17
Bus Arbitration Control................................................................................ 3-22
Bus Error and Halt Operation ..................................................................... 3-30
Asynchronous Operation ............................................................................ 3-35
Synchronous Operation .............................................................................. 3-38
The Relationship of DTACKB, BERRB, and HALTIB ................................. 3-42
Privilege Modes ............................................................................................ 4-1
Exception Processing Description .............................................................. 4-11
Address Output Enable (AOEB) ................................................................. 2-8
Control Output Enable (COEB) .................................................................. 2-8
Data Output Enable (DOEB) ...................................................................... 2-8
Function Codes (FC2–FC0) ....................................................................... 2-8
Address Three-State Control (TSCAE) ...................................................... 2-9
Stop Instruction Indicator (STOP)............................................................... 2-9
Interrupt Pending (IPENDB) ....................................................................... 2-9
CPU Pipe Refill (REFILLB)......................................................................... 2-9
Microsequencer Status Indication (STATUSB) .......................................... 2-9
Read Cycle ................................................................................................. 3-2
Write Cycle ................................................................................................. 3-8
Read-Modify-Write Cycle.......................................................................... 3-13
Requesting the Bus .................................................................................. 3-18
Receiving the Bus Grant........................................................................... 3-18
Acknowledgment of Mastership (3-Wire Bus Arbitration Only)................. 3-19
Bus Error Operation.................................................................................. 3-30
Retrying the Bus Cycle ............................................................................. 3-32
Halt Operation .......................................................................................... 3-32
Double Bus Fault ...................................................................................... 3-35
Supervisor Mode ........................................................................................ 4-2
User Mode .................................................................................................. 4-2
Privilege Mode Changes ............................................................................ 4-2
Reference Classification............................................................................. 4-3
CPU Space Cycle....................................................................................... 4-3
Exception Vectors..................................................................................... 4-11
Interrupt Acknowledge Cycle.................................................................... 4-3
Autovectored Interrupt Acknowledge Cycle ............................................. 4-7
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Exception Processing
Go to: www.freescale.com
Bus Operation
Section 3
Section 4
MOTOROLA