MC68EC000 Motorola, MC68EC000 Datasheet - Page 128

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

6.12 EXCEPTION PROCESSING EXECUTION TIMES
Table 6-14 lists the timing data for exception processing. The numbers of clock periods
include the times for all stacking, the vector fetch, and the fetch of the first instruction of the
handler routine. The total number of clock periods, the number of read cycles, and the num-
ber of write cycles are shown in the previously described format. The number of clock peri-
ods, the number of read cycles, and the number of write cycles, respectively, must be added
to those of the effective address calculation where indicated by a plus sign (+).
MOTOROLA
MOVEP
+ Add effective address calculation time.
Instruction
Table 6-13. Move Peripheral Instruction Execution Times
Table 6-12. Miscellaneous Instruction Execution Times
Table 6-14. Exception Processing Execution Times
Address Error
Bus Error
CHK Instruction
Divide-by-Zero
Illegal Instruction
Interrupt
Privilege Violation
RESET**
Trace
TRAP Instruction
TRAPV Instruction
+Add effective address calculation time.
*The interrupt acknowledge cycle is assumed to take four
clock periods.
**Indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Word
Long
Size
Exception
Go to: www.freescale.com
Register
16(2/2)
24(2/4)
Memory
Periods
40(4/3)+
38(4/3)+
44(5/3)*
50(4/7)
50(4/7)
34(4/3)
34(4/3)
40(6/0)
34(4/3)
34(4/3)
34(5/3)
16-Bit Instruction Execution Times
Memory
16(4/0)
24(6/0)
Register
6-9