MC68EC000 Motorola, MC68EC000 Datasheet - Page 6

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.6
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.5
2.5.1
2.5.2
2.5.3
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
MOTOROLA
FlexCore Integrated Processors ................................................................... 1-2
Development Cycle....................................................................................... 1-5
Programming Model...................................................................................... 1-7
Data Types and Addressing Modes.............................................................. 1-9
Data Organization ....................................................................................... 1-10
Instruction Set Summary............................................................................. 1-11
Address Bus (A31–A0) ................................................................................. 2-1
Data Bus (D15–D0)....................................................................................... 2-1
Clock (CLKI, CLKO)...................................................................................... 2-1
Asynchronous Bus Control ........................................................................... 2-3
Bus Arbitration Control.................................................................................. 2-5
Interrupt Control (IPLB2–IPLB0) ................................................................... 2-5
System Control ............................................................................................. 2-6
FlexCore Advantages ................................................................................. 1-4
FlexCore Module Types.............................................................................. 1-4
Data Registers .......................................................................................... 1-10
Address Registers .................................................................................... 1-10
Data Organization In Memory................................................................... 1-10
Address Strobe (ASB) ................................................................................ 2-3
Read/Write (RWB) and Early Read/Write (ERWB)..................................... 2-3
Upper and Lower Data Strobes (UDSB, LDSB), and Data Strobe (DSB) .. 2-4
Data Transfer Acknowledge (DTACKB) ..................................................... 2-4
Data Transfer Size (SIZ1–SIZ0) ................................................................. 2-4
Read-Modify-Write (RMCB) ........................................................................ 2-5
Bus Request (BRB) .................................................................................... 2-5
Bus Grant (BGB)......................................................................................... 2-5
Bus Grant Acknowledge (BGACKB)—3-Wire Protocol Only ...................... 2-5
Bus Error (BERRB)..................................................................................... 2-6
Reset External/Internal (RESETIB, RESETOB) ......................................... 2-6
Halt External/Internal (HALTIB, HALTOB).................................................. 2-6
Mode (MODE)............................................................................................. 2-7
Disable Control (DISB) ............................................................................... 2-7
Test Mode (TEST) ...................................................................................... 2-7
Test Clock (TESTCLK) ............................................................................... 2-7
Autovector (AVECB) ................................................................................... 2-8
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
TABLE OF CONTENTS
Go to: www.freescale.com
Signal Description
Section 1
Overview
Section 2
vii