MC68EC000 Motorola, MC68EC000 Datasheet - Page 63

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
3.3 BUS ARBITRATION CONTROL
The asynchronous bus arbitration signals are synchronized before being used internally.
See 3.5 Asynchronous Operation for more information on the synchronization of these
signals.
Bus arbitration control is implemented with a finite state machine. State diagram (a) in Figure
3-18 applies for 3-wire bus arbitration and state diagram (b) applies for 2-wire bus arbitra-
tion, in which BGACKB is permanently negated internally or externally. The same finite state
machine is used, but it is effectively a three-state machine because BGACKB is always
negated.
In Figure 3-18, input signals R (bus request internal) and A (bus grant acknowledge internal)
are the internally synchronized versions of BRB and BGACKB. The BGB output is shown as
G (bus grant), and the internal three-state control signal is shown as T (three-state control
to bus control logic). If T is true, the address, data, and control buses are placed in the high-
impedance state when ASB is negated. All signals are shown in positive logic (active high),
regardless of their true active voltage level. State changes (valid outputs) occur on the next
rising edge of the clock after the internal signal is valid.
A timing diagram of the bus arbitration sequence during an SCM68000 bus cycle is shown
in Figure 3-19 and Figure 3-22. The bus arbitration timing while the bus is inactive (e.g., the
SCM68000 is performing internal operations for a multiply instruction) is shown in Figure 3-
20 and Figure 3-23.
When a bus request is made after the SCM68000 has begun a bus cycle and before ASB
has been asserted (S0), the special sequence shown in Figure 3-21 and Figure 3-24
applies. Instead of being asserted on the next rising edge of clock, BGB is delayed until the
second rising edge following its internal assertion.
Figure 3-19, Figure 3-20, and Figure 3-21 apply for 3-wire bus arbitration. Figure 3-22, Fig-
ure 3-23, and Figure 3-24 apply for 2-wire bus arbitration.
3-22
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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