MC68EC000 Motorola, MC68EC000 Datasheet - Page 56

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

STATE 2
STATE 3
STATE 4
CASE READ 1: Only DTACK is received.
STATE 5
STATE 6
STATE 7
STATES 8–11
STATE 12
STATE 13
STATE 14
STATE 15
STATE 16
MOTOROLA
On the rising edge of state 2 (S2), the SCM68000 asserts ASB, UDSB or LDSB, and DSB.
During state 3 (S3), no bus signals are altered.
During state 4 (S4), the SCM68000 waits for a cycle termination signal (DTACKB or
BERRB). If neither termination signal is asserted before the falling edge at the end of S4,
the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is as-
serted. See 3.7 The Relationship of DTACKB, BERRB, and HALTIB for a description
of how DTACKB and BERRB interact.
During state 5 (S5), no bus signals are altered.
During state 6 (S6), data from the device is driven onto the data bus.
On the falling edge of the clock entering state 7 (S7), the SCM68000 accepts data from
the device and negates UDSB or LDSB, and DSB. The device negates DTACKB at this
time.
The bus signals are unaltered during state 8 (S8)through state 11 (S11), during which the
arithmetic logic unit makes appropriate modifications to the data.
The write portion of the cycle starts in state 12 (S12). The valid function codes on FC2–
FC0, the address bus lines, ASB, RWB, and ERWB remain unaltered.
During state 13 (S13), ERWB is driven to a logic low.
On the rising edge of state 14 (S14), the SCM68000 drives RWB to a logic low.
During state 15 (S15), the data bus is driven out of the high-impedance state as data is
placed on the bus.
During state 16 (S16), the SCM68000 waits for a cycle termination signal (DTACKB or
BERRB). If neither termination signal is asserted before the falling edge at the end of S16,
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Bus Operation
3-15