MC68EC000 Motorola, MC68EC000 Datasheet - Page 60

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MC68EC000

Manufacturer Part Number
MC68EC000
Description
Core Processor (SCM 68000)
Manufacturer
Motorola
Datasheet

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BGB can be routed through a daisy-chained network or through a specific priority-encoded
network. Any method of external arbitration that observes the protocol can be used.
3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only)
Upon receiving BGB, the requesting device waits until ASB, DTACKB, and BGACKB are
negated before asserting BGACKB. The negation of ASB indicates that the previous bus
master has completed its cycle. (No device is allowed to assume bus mastership while ASB
is asserted.) The negation of BGACKB indicates that the previous master has released the
bus. The negation of DTACKB indicates that the previous slave has terminated the connec-
tion to the previous master. (In some applications, DTACKB might not be included in this
function; general-purpose devices would be connected using ASB only.) When BGACKB is
asserted, the asserting device is bus master until it negates BGACKB. BGACKB should not
be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus
by negating BGACKB.
The bus request from the granted device should be negated after BGACKB is asserted. If
another bus request is pending, BGB is reasserted within a few clocks, as described in 3.3
Bus Arbitration Control . The SCM68000 does not perform any external bus cycles before
reasserting BGB.
MOTOROLA
1) NEGATE BUS GRANT (BGB)
1) ASSERT BUS GRANT (BGB)
ACKNOWLEDGE RELEASE OF
REARBITRATE OR RESUME
GRANT BUS ARBITRATION
PROCESSOR OPERATION
BUS MASTERSHIP
Figure 3-15. 2-Wire Bus Arbitration Cycle Flowchart
PROCESSOR
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
1) ASSERT BUS REQUEST (BRB)
1) NEGATE BUS REQUEST (BRB)
1) EXTERNAL ARBITRATION DETER-
2) NEXT BUS MASTER WAITS FOR
3) PERFORM DATA TRANSFERS (READ
MINES NEXT BUS MASTER
CURRENT CYCLE TO COMPLETE
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO-
CESSOR USES
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
Bus Operation
3-19

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