MC68EC000 Motorola, MC68EC000 Datasheet - Page 126

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

6.8 CONDITIONAL INSTRUCTION EXECUTION TIMES
Table 6-9 lists the timing data for the conditional instructions. The total number of clock peri-
ods, the number of read cycles, and the number of write cycles are shown in the previously
described format.
6.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES
Table 6-10 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective
address (LEA), push effective address (PEA), and move multiple registers (MOVEM)
instructions. The total number of clock periods, the number of read cycles, and the number
of write cycles are shown in the previously described format.
6.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 6-11 lists the timing data for multiprecision instructions. The number of clock periods
includes the time to fetch both operands, perform the operations, store the results, and read
the next instructions. The total number of clock periods, the number of read cycles, and the
number of write cycles are shown in the previously described format.
MOTOROLA
JMP
JSR
LEA
PEA
MOVEM
M
MOVEM
R
n is the number of registers to move.
*The size of the index register (Xn) does not affect the instruction's execution time.
Instruction Size
M
R
Table 6-10. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times
Word
Word
Long
Long
—
—
—
—
Bcc
BRA
BSR
CHK (No Trap)
DBcc
TRAPV
Instruction
16(2/2)
12(1/2)
(3+n/0)
12+4n
12+8n
(3+2n/
8(2/0)
4(1/0)
(2/2n)
8+4n
8+8n
(An)
(2/n)
0)
Table 6-9. Conditional Instruction Execution Times
(3+n/0)
(3+n/0)
12+4n
12+8n
(An)+
—
—
—
—
—
—
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
–(An) (d 16 ,An) (d 8 ,An,Xn)+ (xxx).W
(2/2n)
8+4n
8+8n
(2/n)
—
—
—
—
—
—
Displacement
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cc false
cc true
(4+2n/0)
Word
Word
Word
10(2/0)
18(2/2)
16(2/2)
(4+n/0)
Byte
Byte
Byte
16+4n
16+8n
12+4n
12+8n
8(2/0)
(3/2n)
—
—
(3/n)
(4+2n/0)
14(3/0)
22(2/2)
12(2/0)
20(2/2)
(4+n/0)
18+4n
18+8n
14+4n
14+8n
(3/2n)
(3/n)
Branch Taken
10(1/0)+
10(2/0)
10(2/0)
10(2/0)
10(2/0)
18(2/2)
18(2/2)
10(2/0)
4(1/0)
(4+2n/0)
10(2/0)
18(2/2)
16(2/2)
(4+n/0)
16+4n
16+8n
12+4n
12+8n
8(2/0)
(3/2n)
—
(3/n)
16-Bit Instruction Execution Times
(5+2n/0)
(xxx).L
12(3/0)
20(3/2)
12(3/0)
20(3/2)
(5+n/0) 16+4n (4n/0) 18+4n (4+n/0)
20+4n
20+8n
16+4n
16+8n
(4/2n)
(4/n)
Branch Not Taken
12(2/0)
12(2/0)
14(3/0)
8(1/0)
—
—
—
—
—
—
(d 16 PC)
(4+2n/0)
10(2/0)
18(2/2)
16(2/2)
16+8n
8(2/0)
—
—
18+8n (4+2n/0)
(d 8 , PC, Xn)*
14(3/0)
22(2/2)
12(2/0)
20(2/2)
—
—
6-7