MC68EC000 Motorola, MC68EC000 Datasheet - Page 47

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
A bus cycle has a minimum of eight states. The various signals are asserted during specific
states of a read cycle, as follows:
STATE 0
3-6
The read cycle starts in state 0 (S0). The SCM68000 places valid function codes on FC2–
FC0, and a valid address on the address bus. RWB and ERWB are driven to logic highs
to identify a read cycle, and TSCAE is driven to a logic high to indicate that the SCM68000
is between bus cycles.
SIZ1–SIZ0
FC2–FC0
DTACKB
D15–D8
A31–A0
TSCAE
ERWB
D7–D0
AOEB
DOEB
RMCB
UDSB
COEB
LDSB
RWB
CLKI
ASB
DSB
Figure 3-6. Word and Byte Read Cycle Timing Diagram for 16-Bit Mode
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
WORD READ
A0=0
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
ODD BYTE READ
A0=1
EVEN BYTE READ
A0=0
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