MC68EC000 Motorola, MC68EC000 Datasheet - Page 82

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
A key consideration when designing in a synchronous environment is the timing for the
assertion of DTACKB and BERRB by an external device. To properly use external inputs,
the SCM68000 must synchronize these signals to the internal clock. The SCM68000 must
sample the external signal and determine whether to consider it high or low during the suc-
MOTOROLA
On the falling edge of the clock entering S3 during a write cycle, the data bus is driven out
of the high-impedance state with the data being written to the accessed device. Parameter
#23 specifies the data assertion delay. In a read cycle, no signal is altered in S3.
Entering the high clock period of S4 during a write cycle, UDSB, LDSB, and DSB are as-
serted on the rising edge of the clock. As in S2 for a read cycle, parameter #9 defines the
assertion delay from the rising edge of S4 for UDSB, LDSB, and DSB. In a read cycle, no
signal is altered by the SCM68000 during S4.
Until the falling edge of the clock at the end of S4 (beginning of S5), no response from any
external device except RESETIB is acknowledged by the SCM68000. If either DTACKB
or BERRB is asserted before the falling edge of S4 and satisfies the input setup time de-
fined by parameter #47, the SCM68000 enters S5 and the bus cycle continues. If either
DTACKB or BERRB is asserted but without meeting the setup time defined by parameter
#47, the SCM68000 may recognize the signal and continue the bus cycle; the result is un-
predictable. If neither DTACKB nor BERRB is asserted before the next falling edge of the
clock, the bus cycle remains in S4, and wait states (complete clock cycles) are inserted
until one of the bus cycle termination conditions is met.
S5 is a low period of the clock, during which the SCM68000 does not alter any signal.
S6 is a high period of the clock, during which data for a read operation is set up relative
to the falling edge (entering S7). Parameter #27 defines the minimum period by which the
data must precede the falling edge. For a write operation, the SCM68000 changes no sig-
nal during S6.
On the falling edge of the clock entering S7, the SCM68000 latches data and negates
ASB and UDSB, LDSB, and DSB during a read cycle. The hold time for these strobes from
this falling edge is specified by parameter #12. The hold time for data relative to the ne-
gation of ASB and UDSB, LDSB, and DSB is specified by parameter #29. For a write cy-
cle, only ASB and UDSB, LDSB, and DSB are negated; timing parameter #12 also
applies.
During a write cycle, on the rising edge of the clock at the end of S7 (which may be the
start of S0 for the next bus cycle), the SCM68000 also places the data bus in the high-
impedance state and drives RWB and ERWB to a logic high. External logic circuitry
should respond to the negation of the ASB and UDSB, LDSB, and DSB by negating
DTACKB and/or BERRB. Parameter #28 is the hold time for DTACKB, and parameter #30
is the hold time for BERRB.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Bus Operation
3-41