MC68EC000 Motorola, MC68EC000 Datasheet - Page 80

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

inserted as required to allow sufficient response time for the external device. The following
state-by-state description of the bus cycle differs from those descriptions in 3.1.1 Read
Cycle and 3.1.2 Write Cycle by including information about the important timing parameters
that apply in the bus cycle states.
Figure 3-33 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous write cycle, including relevant timing parameters, is
shown in Figure 3-34.
STATE 0
MOTOROLA
The bus cycle starts in S0, during which the clock is high. At the rising edge of S0, the
function code for the access is driven externally. Parameter #6A defines the delay from
this rising edge until the function codes are valid. The address of the accessed device is
driven externally with an assertion delay defined by parameter #6. The RWB and ERWB
signals are driven to logic high; parameter #18 defines the delay from the same rising
edge to the transition of RWB. The minimum value for parameter #18 applies to a read
UDSB and/or LDSB
FC2–FC0
DTACKB
and DSB
A31–A0
D15–D0
TSCAE
ERWB
CLKI
RWB
ASB
Freescale Semiconductor, Inc.
6A
S0
6
Figure 3-33. Synchronous Read Cycle
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
18
C6
9
S1
Go to: www.freescale.com
S2
S3
47
47
S4
S5
27
S6
S7
12
S0
29
28
28
Bus Operation
3-39