MC68EC000 Motorola, MC68EC000 Datasheet - Page 52

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MC68EC000

Manufacturer Part Number
MC68EC000
Description
Core Processor (SCM 68000)
Manufacturer
Motorola
Datasheet

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The descriptions of the eight states of a write cycle are as follows:
STATE 0
STATE 1
MOTOROLA
The write cycle starts in state 0 (S0). The SCM68000 places valid function codes on FC2–
FC0 and a valid address on the address bus. RWB and ERWB are driven to a logic high.
TSCAE is driven to a logic high to indicate that the SCM68000 is between bus cycles.
Entering state 1 (S1), the SCM68000 drives TSCAE and ERWB to logic lows.
Figure 3-11. Word and Byte Write Cycle Timing Diagram for 16-Bit Mode
SIZ1–SIZ0
FC2–FC0
DTACKB
D15–D8
A31–A0
TSCAE
D7–D0
ERWB
COEB
DOEB
RMCB
UDSB
AOEB
LDSB
RWB
CLKI
ASB
DSB
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
Freescale Semiconductor, Inc.
WORD WRITE
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
A0=0
Go to: www.freescale.com
ODD BYTE WRITE
A0=1
EVEN BYTE WRITE
A0=0
Bus Operation
3-11

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