MC68EC000 Motorola, MC68EC000 Datasheet - Page 57

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
CASE WRITE 1: DTACKB is received alone or with BERRB (see 3.4 Bus Error and Halt
Operation ).
STATE 17
STATE 18
STATE 19
CASE READ 2: DTACKB and BERRB are received (see 3.4 Bus Error and Halt Opera-
tion ).
STATE 5
STATE 6
STATE 7
STATES 8–10
STATE 11
CASE READ 3: Only BERRB is received (see 3.4 Bus Error and Halt Operation ).
STATES 5–8
STATE 9
STATE 10
3-16
the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is as-
serted. Also, on the rising edge of S16, the SCM68000 asserts UDSB or LDSB, and DSB.
During state 17 (S17), no bus signals are altered.
During state 18 (S18), no bus signals are altered.
On the falling edge of the clock entering state 19 (S19), the SCM68000 negates ASB,
UDSB or LDSB, and DSB. As the clock rises at the end of S19, the SCM68000 places the
data bus in the high-impedance state and drives RWB and ERWB to a logic high. The de-
vice negates DTACKB or BERRB at this time.
During state 5 (S5), no bus signals are altered.
During state 6 (S6), no bus signals are altered and data from the device is ignored.
During state 7 (S7), UDSB or LDSB, and DSB are negated.
The bus signals are unaltered during state 8 (S8) through state 10 (S10).
During state 11 (S11), ASB, is negated. The cycle terminates without the write portion of
the cycle.
The bus signals are unaltered during state 5 (S5) through state 8 (S8).
During state 9 (S9), UDSB or LDSB, and DSB are negated.
During state 10 (S10), no bus signals are altered.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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