MC68EC000 Motorola, MC68EC000 Datasheet - Page 105

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
Interrupt requests should be maintained on the interrupt control signals IPLB2–IPLB0 until
the interrupt acknowledge bus cycle is initiated to guarantee that the interrupt will be recog-
nized.
4.3.2.1 LEVEL SEVEN INTERRUPTS. Level seven interrupts are handled differently than
interrupt levels one through six. A level seven interrupt is a nonmaskable interrupt; therefore,
a seven in the interrupt mask does not disable a level seven interrupt.
Level seven interrupts are edge triggered by a transition from a lower priority request to the
level seven request, as opposed to interrupt levels one through six, which are level sensitive.
Therefore, if IPLB2-IPLB0 remain at level seven, the SCM68000 will only recognize one lev-
el seven interrupt since only one transition from a lower level request to a level seven re-
quest occurred. For the processor to recognize a level seven interrupt followed by another
level seven interrupt, one of the two following sequences must occur:
For more information on SCM68000 interrupts, see the application note A Discussion of
Interrupts for the MC68000 (AN1012).
4.3.2.2 UNINITIALIZED INTERRUPT. Under normal conditions, an interrupting device pro-
vides the SCM68000 with an interrupt vector number and asserts data transfer acknowledge
(DTACKB), or asserts autovector (AVECB), or bus error (BERRB) during an interrupt
acknowledge cycle by the SCM68000. If the interrupting M68000 Family peripheral has not
been initialized, it will provide the uninitialized interrupt vector number ($0F). This response
conforms to a uniform way to recover from a programming error.
4.3.2.3 SPURIOUS INTERRUPT. During the interrupt acknowledge cycle, if no device
responds by asserting DTACKB or AVECB, BERRB should be asserted to terminate the
vector acquisition. The SCM68000 separates the processing of this error from bus error by
forming a short format exception stack and fetching the spurious interrupt vector instead of
the bus error vector. The SCM68000 then proceeds with the usual exception processing.
4-20
1. The interrupt request level on the interrupt control pins changes from a lower request
2. The interrupt request level on the interrupt control pins changes from a lower request
level to level seven and remains at level seven until the interrupt acknowledge bus cy-
cle begins. Later, the interrupt request level returns to a lower interrupt request level
and then back to level seven, causing a second transition on the interrupt control lines.
level to level seven and remains at level seven. If the interrupt handling routine for the
level seven interrupt lowers the interrupt mask level, a second level seven interrupt will
be recognized even though no transition has occurred on the interrupt control pins. Af-
ter the level seven interrupt handling routine completes, the SCM68000 will compare
the interrupt mask level to the interrupt request level on IPLB2-IPLB0. Since the inter-
rupt mask level will be lower than the requested level, the interrupt mask will be set
back to level seven. The level seven request on IPLB2-IPLB0 must be held until the
second interrupt acknowledge bus cycle has begun to insure that the interrupt is rec-
ognized.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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