MC68EC000 Motorola, MC68EC000 Datasheet - Page 116

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

5.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES
Table 5-11 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective
address (LEA), push effective address (PEA), and move multiple registers (MOVEM)
instructions. The total number of clock periods, the number of read cycles, and the number
of write cycles are shown in the previously described format.
5.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 5-12 lists the timing data for multiprecision instructions. The numbers of clock periods
include the times to fetch both operands, perform the operations, store the results, and read
the next instructions. The total number of clock periods, the number of read cycles, and the
number of write cycles are shown in the previously described format.
MOTOROLA
JMP
JSR
LEA
PEA
MOVEM
M
MOVEM
R
*The size of the index register (Xn) does not affect the instruction's execution time.
n is the number of registers to move.
Instruction Size
M
R
Table 5-11. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times
Word
Word
Long
Long
—
—
—
—
Bcc
BRA
BSR
DBcc
CHK
TRAPV
+ Add effective address calculation time for word operand.
* Indicates maximum base value.
Instruction
(6+2n/0)
(6+4n/0)
24+16n
16+16n
16(4/0)
32(4/4)
24(2/4)
24+8n
16+8n
8(2/0)
(4/2n)
(4/4n)
Table 5-10. Conditional Instruction Execution Times
(An)
(6+2n/0)
(6+4n/0)
Freescale Semiconductor, Inc.
24+16n
24+8n
(An)+
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
—
—
—
—
—
—
Displacement
16+16n
16+8n
(4/2n)
(4/4n)
–(An)
—
—
—
—
—
—
Go to: www.freescale.com
cc False
cc True
Word
Word
Word
Byte
Byte
Byte
—
—
(d 16 ,An) (d 8 ,An,Xn)+ (xxx).W
(8+2n/0)
(8+4n/0)
32+16n
24+16n
18(4/0)
34(4/4)
16(4/0)
32(4/4)
32+8n
24+8n
(6/2n)
(6/4n)
(8+2n/0)
(8+4n/0)
34+16n
26+16n
22(4/0)
38(4/4)
20(4/0)
36(4/4)
Trap or Branch
34+8n
26+8n
(6/2n)
68(8/6)+*
66(10/6)
18(4/0)
18(4/0)
18(4/0)
18(4/0)
34(4/4)
34(4/4)
18(4/0)
Taken
—
(10+n/0)
(8+4n/0)
32+16n
24+16n
18(4/0)
34(4/4)
16(4/0)
32(4/4)
32+8n
24+8n
(6/2n)
(8/4n)
8-Bit Instruction Execution Times
Trap or Branch
(10+2n/0)
Not Taken
(8+4n/0)
40+16n
32+16n
(xxx).L
24(6/0)
40(6/4)
24(6/0)
40(6/4)
14(2/0)+
40+8n
32+8n
(8/2n)
(6/4n)
12(2/0)
20(4/0)
20(4/0)
26(6/0)
8(2/0)
—
—
—
—
(d 16 PC)
(8+2n/0)
(8+4n/0)
32+16n
18(4/0)
34(4/4)
16(4/0)
32(4/4)
32+8n
—
—
(d 8 , PC,
(8+2n/0)
(8+4n/0)
34+16n
22(4/0)
32(4/4)
20(4/0)
36(4/4)
34+8n
Xn)*
—
—
5-7