MC68EC000 Motorola, MC68EC000 Datasheet - Page 81

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
STATE 1
STATE 2
3-40
cycle preceded by a write cycle; this value is the maximum hold time for a logic low on
RWB beyond the initiation of the read cycle. The TSCAE signal is driven to a logic high.
Parameter #C6 defines the delay from the rising edge of the clock to the assertion of
TSCAE.
Entering S1, a low period of the clock, TSCAE is driven to a logic low. During a write, the
ERWB signal is driven to a logic low with an assertion delay defined by parameter #C3.
On the rising edge of S2, a high period of the clock, ASB is asserted. During a read cycle,
UDSB, LDSB, and DSB are also asserted at this time. Parameter #9 defines the assertion
delay for these signals. For a write cycle, the RWB signal is driven to a logic low with a
delay defined by parameter #20.
UDSB and/or LDSB
FC2–FC0
and DSB
DTACKB
A31–A0
D15–D0
TSCAE
ERWB
CLKI
RWB
ASB
6A
6
S0
Figure 3-34. Synchronous Write Cycle
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
18
For More Information On This Product,
C6
S1
C3
Go to: www.freescale.com
23
S2
9
20
S3
9
47
S4
S5
12
S6
S7
53
S0
28
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