MC68EC000 Motorola, MC68EC000 Datasheet - Page 38

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

2.9.2 Address Three-State Control (TSCAE)
This active-high output signal is asserted between bus cycle accesses of the SCM68000.
2.9.3 Stop Instruction Indicator (STOP)
This output line pulses at one fourth the rate of the CLKI signal with an active time of one
clock period when the STOP instruction is executed.
2.9.4 Interrupt Pending (IPENDB)
This active-low output signal indicates a valid interrupt has been recognized.
2.9.5 CPU Pipe Refill (REFILLB)
This active-low output signal is asserted for one clock period to indicate that a refill of the
CPU pipe is occurring due to a change in program flow. This is used for emulator support.
2.9.6 Microsequencer Status Indication (STATUSB)
This active-low output signal indicates microsequencer status and is used for emulator sup-
port. The number of clock cycles for which this signal is asserted indicates the status of the
SCM68000. When the SCM68000 approaches an instruction boundary, this signal is nor-
mally asserted for one clock cycle. Table 2-7 indicates exceptions that are indicated by the
assertion of this signal for more than one cycle.
2.10 MULTIPLEXING PINS
When a design is implemented, certain pins need to be multiplexed to the pads for testing
purposes. Motorola recommends that all the pins on the SCM68000 be multiplexed to offer
a means for testing the processor with test vectors provided by Motorola. This will provide
maximum fault coverage. Varying degrees of fault coverage can be obtained depending on
which pins the user does or does not multiplex.
MOTOROLA
One Clock
Two Clocks
Three Clocks
Continuously
Asserted For
Sequencer at instruction boundary - will begin execution of next instruction
Sequencer at instruction boundary - will not begin the next instruction immediately due to:
• Pending Interrupt Exception or
• Pending Trace Exception or
• Illegal Instruction Exception or
• Pending Breakpoint Instruction Exception or
• Privileged Instruction Exception
Exception processing to begin for:
• Bus Error or
• Address Error or
• A-line Instruction or
• Spurious Interrupt or
• Illegal Instruction or
• Privileged Instruction or
• Auto vectored Interrupt or
• F-line Instruction
Core is:
• Halted
• Reset
Freescale Semiconductor, Inc.
Table 2-7. Status Indication Exceptions
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Indicates
Signal Description
2-9